EMZETT.Bus Systems
In short: Internal data connections in a computer over which several components jointly exchange data — e.g. the PCIe bus between the CPU/chipset and expansion cards.
In more detail: A bus connects not just two but potentially several participants over the same lines, which saves on wiring but splits bandwidth among the participants. Well-known examples are PCIe (expansion cards), USB (peripherals) and internal memory buses.
In Depth
Why a bus at all?
The alternative to a bus would be direct point-to-point wiring between every single component — with n participants, that would theoretically need a dedicated line for every possible pair, which with many participants would quickly lead to an impractical tangle of cables and enormous space requirements on the board. A bus solves this by having all connected devices share the same lines and using a protocol to regulate who’s allowed to send when (e.g. via arbitration or fixed time slots). The price for that: the available bandwidth has to be split among all active participants — while one participant is sending, the others have to wait.
From a shared bus to a switched connection
Modern bus systems like PCIe are therefore increasingly built as “switched” point-to-point connections with several parallel lanes, rather than as a classic, shared bus in the original sense: every device effectively gets its own, dedicated connection to a central switch chip that intelligently forwards traffic — the word “bus” has stuck around for historical reasons, even though the physical architecture no longer matches the original “everyone shares one line” principle.
Bus levels in a computer
Inside a computer there are several levels of buses with very different speeds and tasks: the memory bus between CPU and RAM (extremely fast, several tens of GB/s, designed for continuous operation with minimal latency), PCIe between the CPU/chipset and expansion cards such as graphics cards or NVMe SSDs (several GB/s per lane, with several lanes possible in parallel), and considerably slower external buses like USB for peripherals (mice, keyboards, external drives). The closer a bus sits to the CPU, the higher its bandwidth typically is and the shorter the physical line lengths, since high clock rates become increasingly susceptible to interference over longer trace distances (electromagnetic interference, signal delay).
Historical bus standards
Earlier PC generations still had considerably more different, slower bus standards for expansion cards (ISA, later PCI, AGP specifically for graphics cards) — PCIe has largely replaced and unified this variety since the mid-2000s, since it scales for both simple network cards and high-end graphics cards (through a different number of parallel lanes, e.g. PCIe x1 through x16).
Bus width and clock rate
A bus’s transmission performance results from the interplay of two quantities: bus width (how many bits are transmitted in parallel at once, e.g. 64 bits for the classic memory bus) and clock rate (how often a new value is applied per second). A wider bus transmits more data per clock cycle, but needs more parallel traces, which have to be exactly the same length and electrically matched (“signal timing”) so that all bits arrive at the receiver simultaneously — at very high clock rates this becomes increasingly demanding technically, which is why modern high-speed buses like PCIe instead rely on few, but very fast-clocked serial lanes, rather than many parallel, slower lines.
The bus as a bottleneck
Since several components share the same bus bandwidth, a bus can become a bottleneck for the overall system, even if the individual connected components would theoretically be faster. A typical example: a very fast NVMe SSD connected via a limited number of PCIe lanes sometimes shares these lanes, depending on the motherboard design, with other expansion cards — if several power-hungry components are active at the same time, the available bandwidth per device can drop below the actually possible maximum speed. For this reason, motherboard manufacturers often specify precisely in their manuals which slots share lanes and under what conditions the available bandwidth is reduced.